1. Field of the Invention
The present invention relates to a memory device and, in particular, to a sense amplifier employed in a semiconductor memory.
2. Description of the Prior Art
FIG. 8 is a circuit diagram showing the configuration of a memory device employing a conventional memory sense amplifier of the grounded-gate type. In the drawing, numerals T1 to T6 and T18 and T19 each denote an N-channel transistor, numerals T21 to T25 each denote a P-channel transistor, numerals I1 and I2 are each an inverter, numeral SL denotes a selector and numeral MB3 is a memory block.
FIG. 2 is a circuit diagram showing the configuration of the selector SL. In the drawing, numerals G30 to G33 each denote a NAND gate, numerals 130 to 135 are each an inverter, numerals T30 to T33 are a group of N-channel transistors having the same channel length and the same channel width and numerals T34 to T37 are another group of N-channel transistors having the same channel length and the same channel width.
FIG. 9 is a circuit diagram showing the configuration of the NOR-type memory block MB3. In the drawing, numerals G60 to G63 each denote an AND gate, numerals I40 to I41 are each an inverter, numerals C1 to C10 are memory-cell transistors having the same channel length and the same channel width, numerals C11 to C16 are other memory-cell transistors having the same channel length and the same channel width and numerals R1 to R12 are wire resistances of word lines W0 to W3. The memory-cell transistors C1 to C16 are each an N-channel transistor forming a memory cell. It should be noted that the memory-cell transistors C11 to C16 each have a threshold voltage equal to or higher than 5V so that, even with the gate voltage thereof varied in the range 0 to 5V, the drain current is smaller than 1 nA and can be said to be almost not flowing.
The operation of the memory device is explained by referring to FIGS. 2, 8 and 9 as follows.
The electric potential VDD of the power supply of the conventional memory device is about 5 V. The memory device is operative when a chip-select signal CS of the memory device shown in FIG. 8 is connected to the electric potential of the ground GND which is referred to hereafter as an "L" level. If the chip-select signal CS is connected to the electric potential VDD of the power supply which is referred to hereafter as an "H" level, on the other hand, the memory device is put in a deselected state and thus not operative. When the chip-select signal CS is put at the "L" level, the P-channel transistor T25 is turned on, pulling up the electric potentials of the sources of the P-channel transistors T24, T23 and T21 connected to the P-channel transistor T25 to the electric potential VDD which is about 5 V. The P-channel transistor T24 and the N-channel transistors T18 and T19 work as a source of voltage supplying an electric potential to the gate of the N-channel transistor T1. To put it in detail, when a current of about 200 .mu.A flows from the drain of the P-channel transistor T24 to the N-channel transistors T18 and T19, the electric potential of the gate of the N-channel transistor T1, that is, the electric potential of a node N3, is about 2.5 V.
On the other hand, the P-channel transistor T23 and the N-channel transistors T4 to T6 work as a source of voltage supplying an electric potential to the gate of the P-channel transistor T21 which serves as a source of current supplying a current to a node N1. The N-channel transistor T4 has the same channel length and the same channel width as the N-channel transistor T1. By the same token, the N-channel transistor T5 has the same channel length and the same channel width as the N-channel transistor T30 employed in the selector SL. Likewise, the N-channel transistor T6 has the same channel length and the same channel width as the memory-cell transistor C1. On the other hand, the P-channel transistor T23 has the same channel length as the P-channel transistor T21 but the channel width of the former is five times that of the latter.
As a result, affected by the current-mirror effect, the drain current of the P-channel transistor T21 is about 150 .mu.A which is about 1/5 of the drain current (referred to hereafter as a memory-cell drain current) of, for example, the memory-cell transistor C1 with the gate voltage thereof set at about 5 V. Since the N-channel transistor T1 is a grounded-gate amplifier, the electric potential at the node N1 is changed in accordance with the magnitude of a current drawn from a node S. The inverter I1 outputs an "L" or "H" level to a node N2 depending upon whether or not the electric potential at the node N1 is higher than a predetermined value. During a precharge period (a period in which the signal level of a clock P1 signal is set at "H"), the inverter I2 and the P-channel transistor T22 precharge one of bit lines B0 to B3 connected to the node S through the nodes N1 and S and the selector SL. The N-channel transistors T2 and T3 work as a positive feedback circuit which draws a current from the node N1, accelerating the change in electric potential when the electric potential at the node N2 changes from "L" to "H".
The inverters I30 and I31 and the NAND gates G30 to G33 employed in the selector SL shown in FIG. 2 constitute an ordinary two-to-four decoder. Depending upon the combination of the "H" or "L" levels of two address input signals A1 and A0, the output of one of the four NAND gates G30 to G33 is reset to the "L" level while the remaining three outputs are all set at the "H" level. The inverters I32 to I35 and the N-channel transistors T30 to T33 couple one of the bit lines B0 to B3 which is associated with the NAND gate reset at the "L" level to the node S. The bit line B0, B1, B2 or B3 coupled to the node S is referred to hereafter as a selected bit line. At that time, the N-channel transistors T34 to T37 reset the electric potentials of the bit lines other than the selected bit line at the ground level, that is, at 0 V.
Assume, for example, that the levels of the address input signals A1 and A0 are set at "H" and reset at "L" respectively. In this case, the output of the NAND gate G32 employed in the selector SL is reset at the "L" level which is inverted by the inverter I34 to an "H" level. As a result, the gate input of the N-channel transistor T32 is set at the "H" level, turning on the N-channel transistor T32. In this state, the bit line B2 is coupled to the node S by the conduction of the N-channel transistor T32. On the other hand, the electric potentials of the bit lines B0, B1 and B3 are pulled down to 0 V. This is because the electric potentials of the gates of the N-channel transistors T34, T35 and T37 are all set at the "H" level, turning on all the N-channel transistors T34, T35 and T37 which, in turn, couple the bit lines B0, B1 and B3 respectively to the electric potential GND of the ground.
By the same token, the inverters I40 and I41 and the AND gates G60 to G63 employed in the memory block MB3 shown in FIG. 9 constitute an ordinary two-to-four decoder with the outputs of the AND gates G60 to G63 connected to the word lines W0 to W3 respectively. Since the gates G60 to G63 are AND gates, however, one of the word lines W0 to W3 specified by the address input signals A3 and A2 is set to the "H" level while the other word lines are reset at the "L" level. The word line W0, W1, W2 or W3 specified by the address input signals A3 and A2 is referred to hereafter as a selected word line. It should be noted that, since the AND gates G60 to G63 input a clock signal P2 as a strobe signal, it is only during the "H"-level period of the clock signal P2 that the selected word line is set at the "H" level. Since the memory-cell transistors C1 to C10 turn on when the word line connected to their gate is set to the "H" level, they draw a memory-cell current from the bit line connected to the drain thereof. On the other hand, the threshold voltage of the memory-cell transistors C11 to C16 is higher than 5 V. As a result, there is no effect on the memory-cell transistors C11 to C16 even if the electric potentials of the word lines connected to their gates are changed.
Next, the operation of the memory device is explained by referring to timing charts shown in FIG. 10.
The explanation begins with a first example of a case in which the levels of the address input signals A3, A2, A1 and A0 are set at "L", "H", "L" and "L", respectively. In this case, the output of the NAND gate G30 employed in the selector SL shown in FIG. 2 is reset at the "L" level which is inverted by the inverter 132 to an "H" level. As a result, the gate input of the N-channel transistor T30 is set at the "H" level, turning on the N-channel transistor T30. In this state, the bit line B0 is the selected bit line connected to the node S by the conduction of the N-channel transistor T30. On the other hand, the electric potential of the AND gate G61 employed in the memory block MB3 shown in FIG. 9 is set at the "H" level, selecting the word line W1 as a selected word line.
As a result, the memory-cell transistor C11 is selected.
First of all, the chip-select signal CS is reset to the "L" level and the address input signals A0 to A3 are received. At the same time, the level of the clock signal P1 changes from "L" to "H". When the chip-select signal CS of the memory device shown in FIG. 8 is reset to the "L" level, the P-channel transistor T25 is turned on, causing the electric potentials of the node N3 and a node N4 to rise to a predetermined value. The selector SL selects the bit line B0 as described above, coupling the bit line B0 to the node S. Since the level of the clock signal P2 in the memory block MB3 is "L", no operation affecting bit lines is carried out.
In this state, the level "H" of the clock signal P1 turns on the P-channel transistor T22, charging up the node N1 toward the 5 V electric potential VDD of the power supply. At the same time, the electric potentials of the node S and the bit line B0 are also charged up to about 1.5 V through the N-channel transistor T1. As a result, the output of the inverter I1, that is, the electric potential of the node N2, is reset to the "L" level. Then, after the bit line B0 has gotten in an all but steady state, the level of the clock signal P1 becomes "L". The period up to this point of time is referred to a precharge period.
As the level of the clock signal P1 turns to "L", causing the P-channel transistor T22 to no longer supply a current, the electric potentials of the nodes N1 and S as well as the bit line B0 slightly decrease. However, the electric potentials decrease only by an amount small enough not to have an effect on the output of the inverter I1. Later on, the drain current of the P-channel transistor T21 causes the electric potentials of the nodes N1 and S as well as the bit line B0 to rise little by little.
Next, the level of the clock signal P2 turns to "H". As a result, the level of the electric potential of the word line W1 changes from "L" to "H". Since the threshold voltage of the gate of the N-channel transistor serving as the memory-cell transistor C11 is higher than 5 V, however, the memory-cell transistor C11 is not turned on, having all but no effect on the bit line B0. Thus, the electric potentials of the node S connected to the bit line B0 and the node N1 do not change and the electric potential of the node N2 remains at the "L" level as it is. As a result, "L" information is read out from the memory device.
The explanation continues to a next example of a case in which the levels of the address input signals A3, A2, A1 and A0 are all reset at "L". In this case, the output of the NAND gate G30 employed in the selector SL is reset at the "L" level which is inverted by the inverter 132 to an "H" level. As a result, the gate input of the N-channel transistor T30 is set at the "H" level, turning on the N-channel transistor T30. In this state, the bit line B0 is the selected bit line coupled to the node S by the conduction of the N-channel transistor T30. On the other hand, the electric potential of only the AND gate G60 employed in the memory block MB3 is set at the "H" level, selecting the word line W0 as a selected word line. As a result, the memory-cell transistor C3 is selected. Also in this case, operations till the level of the clock signal P2 turns to "H" are the same as the first example described above. As the level of the clock signal P2 turns to "H", the output of the AND gate G60 and the electric potential of the word line W0 turn to the "H" level. As a result, the gate of the N-channel transistor serving as the memory-cell transistor C3 is raised, turning on the memory-cell transistor C3 which draws a memory-cell current from the bit line B0.
Since the magnitude of this current is five times that of the drain current of the P-channel transistor T21, the electric potential of the node N1 gradually decreases. The electric potentials of the node S and the bit line B0 also decrease but, since the capacitance of the bit line B0 is much larger than that of the node N1, the drop in electric potential on the bit line B0 is small. When the electric potential of the node N1 becomes equal to or lower than a predetermined value, the level of the output of the inverter I1 changes from "L" to "H". In this state, since the N-channel transistor T3 is turned on at a point of time the level of the clock signal P1 turns to "L", the N-channel transistor T2 is turned on, thus drawing a current much larger than the memory-cell current from the node N1. As a result, the drop of the electric potential of the node N1 is accelerated and the rise of the electric potential of the node N2 from "L" to "H" is also accelerated. Thus, "H" information is read out from the memory device.
The following is description of an example of a case in which the levels of the address input signals A3, A2, A1 and A0 are set at "L", "L", "H" and "H", respectively. In this case, using the same reasoning as those of the two examples described above, the selected bit line and the selected word line are found to be B3 and W0 respectively, selecting the memory-cell transistor C10. The operations in this case are all but the same as the case described above in which the memory-cell transistor C3 is selected except that the selected bit line is now B3. In this case, however, due to the resistances of wire resistors R4, R8 and R12 in conjunction with the gate capacitances of the memory-cell transistors C5, C15 and C10, the timing with which the electric potential of the gate of the memory-cell transistor C10 rises much lags behind the word line W0. As a result, the timing with which the electric potentials of the bit line B3 and the nodes S and N1 decrease lags as well and, in its turn, the change of the electric potential of the node N2 also lags as shown in the drawing. As a result, "H" information is read out from the memory device but the time it takes to read the information, that is, the access time, is longer than that of the previous example.